How silicon programs are run, and why they slip.
Plain answers to the questions engineering and operations leaders ask about holding a silicon program to its date.
Guides
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What is silicon program management?
Silicon program management is the work of holding every team, tool and supplier on a chip, equipment or qualification program to one date. Here is what it covers and why it is hard.
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Why tape-outs slip: the anatomy of a schedule slip
Most tape-out slips are not engineering failures. They are changes that were visible in a tool on day one and reached the people who could act two weeks later. Here is how a slip actually unfolds.
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First-silicon success is at a 20-year low. What it costs you
Only 14% of chip projects achieve first-silicon success, according to the 2024 Siemens / Wilson Research Group study. Here is what a re-spin costs and what moves the odds.
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Firmware readiness: keeping software on the silicon date
When silicon slips, firmware usually keeps working to the old date. Here is why firmware and silicon drift apart, and how to hold bring-up software, drivers and SDKs to the same date as the chip.
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Beta-tool programs: holding an equipment platform to its insertion window
A new semiconductor equipment platform has one deadline that does not move: the customer's insertion window. Here is how beta-tool programs slip, and what tracks the date across PLM, software and suppliers.
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Qualification tracking for foundries and OSATs
Foundries, OSATs and test houses run dozens of customer qualifications at once, and are paid only after sign-off. Here is how quals slip, and how to make sure the customer hears it from you first.
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Air-gapped AI for semiconductor design floors
Advanced-node, ITAR and foundry-restricted programs cannot send data to a cloud model. Here is what air-gapped AI means, what it needs, and how it runs on a sealed appliance.
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The authority envelope: how much should AI be allowed to do on a chip program?
The useful question about AI on an engineering program is not whether to trust it, but what exactly it may do without asking. Here is how to set that boundary.
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Decision receipts: auditing what an AI did on your program
If an AI takes an action on an engineering program, someone will eventually ask who approved it and why. Here is what a usable audit record contains.
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The coordination tax: how much engineering time goes to finding out what is true
Roughly a third of engineering time on a large program goes to coordination, by industry estimate. Here is what that is, what it costs, and how to work it out for your own program.
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Program memory: why the next chip program repeats the last one's mistakes
Every chip team learns hard lessons and loses most of them when the program ends. Here is what a program memory is, and what it can answer.
Use cases
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How to catch a supplier delay before it moves your tape-out
A late IP delivery is announced in an email. Here is how that email turns into a missed tape-out, and the four steps that stop it.
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Tape-out readiness: how to answer “are we ready?” in minutes
A tape-out readiness review usually runs on slides that took days to build. Here is what readiness really consists of, and how to read it from the tools instead.
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Verification coverage closure: how to see it falling behind early
Coverage rarely fails suddenly. The curve flattens weeks before anyone calls it late. Here is how to forecast coverage closure against the date.
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How to run a program review on exceptions instead of status
Most program reviews spend two hours establishing what is true. Here is how to make the review twenty minutes about what needs deciding.
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Root-cause analysis for a missed silicon milestone
After a slip, the usual finding is the last visible symptom. Here is how to find the decision that actually caused it.
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What to tell a customer when a qualification slips
A qualification delay is survivable. A customer finding out from a late shipment is not. Here is what to send, and when.
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ECO impact: tracing an engineering change across a chip program
A late engineering change order looks small where it is made and expensive where it lands. Here is how to see the whole impact before approving it.
Comparisons
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Jira for chip design: what it holds, and what it can't see
Most chip teams run Jira. It tracks tickets well and cannot see a coverage curve, a timing report or a foundry email. Here is where it fits on a silicon program and what sits above it.
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AI Employees, agents and copilots in semiconductor engineering
Copilots help one engineer. Agents do one task inside one tool. An AI Employee holds a role in a program, with an identity, a scope and a record. Here is the difference and why it matters for governance.
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Can ChatGPT or Claude manage a chip program?
General AI models are capable and cannot run a silicon program on their own. Here is what they lack — and it is not intelligence.
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EDA AI agents and the program layer: who holds the date?
EDA vendors now ship AI agents that do engineering work. They are useful, and they stop at the edge of their own tools. Here is what sits above them.
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Program management tools for semiconductor teams: what each one owns
Jira, PLM, ERP, EDA dashboards and spreadsheets each own part of a silicon program. None owns the date. Here is the map.
Briefings
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AI regulation for engineering programs: EU AI Act, NIST AI RMF and ISO 42001
Three frameworks now shape how AI may be used inside engineering organisations. Here is what each one is, and what they ask for in common.
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AI coding agents in firmware teams: who holds them to the release?
Firmware organisations now run dozens of AI coding agents. They produce a great deal of code and none of them answers for the release date.